The invention relates generally to a semiconductor device and a method of fabricating the same and, more particularly, to a semiconductor device in which gate patterns are formed, and a method of fabricating the same.
In general, in a flash memory semiconductor device, a gate pattern is formed by patterning a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, and a gate electrode.
FIG. 1 is a sectional view of a semiconductor device for forming a gate pattern of the device in the prior art.
Referring to FIG. 1, a tunnel dielectric layer 11, a conductive layer for a floating gate 12, a dielectric layer 13, a conductive layer for a control gate 14, a gate electrode layer 15, and a hard mask layer 16 are sequentially stacked over a semiconductor substrate 10. The hard mask layer 16 is patterned, and the gate electrode layer 15 is patterned by an etch process employing the patterned hard mask layer.
Generally, in the case in which a tungsten silicide (WSix) layer is used as a gate electrode layer in semiconductor devices of 50 nm or less, resistance (Rs) of word lines is increased due to high resistivity of the tungsten silicide (WSix) layer itself and therefore the program and read speeds are lowered. To solve the problems, the thickness of the tungsten silicide (WSix) layer should be increased. However, this method makes a patterning process of the word lines difficult and void may occur within isolation layers that electrically isolate the word lines. Accordingly, research has been done on a method of forming the gate electrode layer using a tungsten (W) layer having lower resistivity than the tungsten silicide (WSix) layer.
However, the tungsten layer is easily oxidized by a thermal process and easily corroded or oxidized and dissolved by a cleaning process in a cleaning process. Accordingly, the tungsten layer greatly limits subsequent processes.